(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a core cell library layout that is free of notch-errors when validated using a Design Rule Check (DRC) program.
(2) Description of the Prior Art
Computer Aided Design (CAD) has been an approach for creating chip designs and layout that has been in use for many years. CAD recognizes and makes use of applying the repetitive nature of chip design and chip layout by using sub-portions of the chip as chip building blocks that have known parameters of design and performance and that are known to be applied for particular functions within a overall functionality of a chip. CAD systems are software based whereby extensive libraries exist that contain the numerous chip-building blocks that are used in the creation of functional chips. The chip sub-functions or building blocks are represented by macros and are contained in a macro cell library. The macros that represent chip sub-functions can be used as input for extensive simulation and verification software that has as objective to analyze expected chip performance and that further allow for the manipulation of chip design parameters thereby effecting and in fact designing ultimate chip performance. It is clear that this approach provides a method that is practical and cost effective, most certainly if this method were to be compared with actually creating various chips of various design characteristics in order to evaluate new chip performance. This latter approach is not practical for many reasons, most notably the cost incurred and the time that is required for such an approach. The method of using CAD support software also makes it possible to realistically evaluate results that can be expected when semiconductor devices are created by different semiconductor vendors that typically have processing conditions and capabilities that vary significantly between vendors. In this manner a particular design can be assigned to the vendor that provides best technical results at the most competitive cost. Further, semiconductor device interconnectivity and the therewith-related aspects of device reliability can be evaluated both at fast turn-around time and at relatively low cost. Answers can in this manner be obtained in a matter of hours, an advantage without which actual design and innovation in a modern semiconductor manufacturing environment would be very difficult if not impossible to maintain. In short: software based support has been used for many years to enable chip design, the evaluation of new chip designs, the evaluation of chip functionality and reliability, the integration of chip sub-functions into larger chip designs and into multi-chip packages. Without such software support functions, semiconductor technology and the advancement of this technology would over the years have suffered serious negative impacts of technical innovation and competitive positioning within the industry.
The processes that are indicated above are, in most cases, aimed at creating mask images that are further used for multiple exposures using photolithographic processes. Using these processes, individual chip building blocks (represented and stored in a macro cell library that is under control of the software support functions) are combined to create combinations that are application specific, that is designs that are aimed ate one specific application of the overall semiconductor device. Most popular and most frequently used for these applications-specific designs are designs of electrically programmable read-only memory (EPROM) cells of which electrically erasable and electrically programmable read-only memory (EEPROM) are a special type, flash EEPROM cells which are specific types of both EPROM and EEPROM cells, standard cells and programmable logic devices. Masks for these devices are customized using CAD technology and are interconnected on an Integrated Circuit to form a partially completed IC.
The creation of a functional IC device typically starts with a description of the logic of the device, which is indicated by the logic functions of the device or the hardware description of the device. The initial logic functions of the device are simulated and verified using the CAD system support functions. After the logic functions have been satisfactorily evaluated in this manner, the hardware layout that implements the logic functions is synthesized. This process uses data that specifically reflects a given technology or a given processing sequence. These latter two pieces of data are typically stored in a data library and include specific parameters that reflect the processing conditions that will be applied to create to device functions. The reference library than contains standard device building blocks (in the form of macrocells) in addition to the specific design and processing rules that are used to combine the various individual sub-functions or device building blocks. The individual device macrocells need to be interconnected, which is performed using a placement and routing function of the CAD support software. The overall design and layout of the (in software) created device is evaluated and functionally simulated thereby again using processing-specific parameters that reflect the interconnect of the macrocells. If after this evaluation the overall device is acceptable in all aspects of the design (functionality, timing characteristics, loading effect including parasitic capacitive and parasitic resistive loading effects, reliability, density, surface area required for the device), the final mask for the device is created. Sample devices are made to validate the created mask and any modifications that may be required as a result of this latter (device) evaluation are implemented in a most cost-effective manner, typically correcting the mask. The final design of a device is typically stored on a macro cell library for future reference.
It is clear that, from a cost point of view, the above indicated cycle to create masks for chip manufacturing needs to be done in a cost-effective manner. This means that, for many of the applied designs, a robust or worst case design is performed and retained as macro cell data in the reference library. This to avoid doing design cycles repetitively for very specific designs. The worst case designs can be used as starting designs for other (specific) designs whereby specific and application dictated design parameters relating to parasitic influences, routing to interconnect device functions, expected processing conditions for the specific device (vendor), actual timing conditions and the like are incorporated into the worst case design. This latter incorporation is aimed at converting the worst-case design to a specific design, the specific design will after this incorporation of specific design conditions as yet need to be evaluated and simulated for the actual, specific fabrication and operating conditions of the device. One of the overriding factors in all of these efforts is that the cost of providing an ultimate mask for a semiconductor device remains competitive since, even though computer programs can be executed at great speed and provide extreme complexity and design support, even computer programs add to the cost of creating a mask whereby specifically simulation runs can require a significant amount of computer run time thereby incurring a significant amount of the cost of the mask. Methods must therefore be provided that simplify the process of creating masks or any other required medium that is used for the creation of cost competitive semiconductor devices. Since CAD methods play an integral role in this process, any method or procedure that advances the state of the art in using the CAD methods is a valuable addition to the support tools that are used for the creation of semiconductor devices.
U.S. Pat. No. 5,754,826 (Gamal et al.) shows a simulation system using Cadence and routing line information.
U.S. Pat. No. 5,550,839 (Buch et al.) shows a mask programmed IC using DRC and merging data.
A principle objective of the invention is to create a database that contains a basic cell library of semiconductor device cells whereby all cells that are contained in the database are free of notch errors in aligning metal layers with via connections.
In accordance with the objectives of the invention a new method has been provided whereby notch errors that can occur in placing via interconnects over layers of metal have been eliminated. A reference database contains all layout data for semiconductor device cells that are used to create the semiconductor devices. A cell layout is read from the reference database and placed on an intermediate data repository. For this cell, valid locations are determined where via connections must be established. Data for a test via are created, the device of the test via is aligned with and placed (xe2x80x9cdroppedxe2x80x9d) over a valid location thereby creating a test site. The purpose of the test site is to validate that the via device is correctly aligned with the metal and without any notch errors. Cases where notch errors occur are identified, for those cases a metal form is created whereby the surface of the metal form is identical with the surface of the notch error. The original metal data is merged with the original via device data and the notch error data, thereby creating new metal data that is free of the notch error. The original metal data and the original test via data and the notch error data are purged, the new metal data are stored on a core cell library for further customer use.